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n2206 / 92502 rm (im) no.7204-1/16 any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before using any sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein. LA70100M overview LA70100M is a secam method chroma-signal processor for vcr applications, realizing reduction in external parts count and adjustment free due to integrated band-pass filter, secam discrimination circuit, and bell filter. features ? integrates all filters required. ? automatic adjustment bell filter fo. ? integrates secam discrimination circuit. specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max 7.0 v allowable power dissipation pd max ta 65 c *440 mw operating temperature topr -10 to +65 c storage temperature tstg -40 to +150 c * 114.3mm 76.1mm 1.6mm when mounted on a grass epoxy pcb. package dimensions unit : mm 3073c-mfp30sd (375mil) [ LA70100M ] orderin g numbe r : enn7204 monolithic linear ic secam chroma-signal processor ic for vcr
LA70100M no.7204-2/16 recommended operating conditions at ta = 25 c parameter symbol conditions ratings unit supply voltage v cc 5.0 v allowable operating voltage range v cc op 4.8 to 5.2 v electrical characteristics at ta = 25 c, v cc = 5v ratings parameter symbol in out conditions min typ max unit recording mode ( t2 = 4.43mhz, 400mvp-p t29 = comp.sync t17 = 0v t4 = open ) rec mode current drain iccr t16 t23 t24 t16 = 4.286mhz, 200mvp-p 40 50 60 ma 4.3mhz bpf characteristics-1 vf4c t16 t18 t9 = 5v t16 = 4.286mhz, 200mvp-p 145 180 215 mvp-p 4.3mhz bpf characteristics-2 gf4l1 t16 t18 same condition as above. however, frequency of t16 is 1.1mhz measure t18 ratio to v4fc. -30 -20 db 4.3mhz bpf characteristics-3 gf4l2 t16 t18 same condition as above. however, frequency of t16 = 2.2mhz -10 -5 db 4.3mhz bpf characteristics-4 gf4h t16 t18 same condition as above. however, frequency of t16 = 7.5mhz -24 -18 db 4.3mhz bell center frequency fblr t18 t20 t18 = 4 to 5mhz, 200mvp-p sw20 = on (3.9k pull-down) ( see notes-1 ) measure during other timing than v-sync 4.243 4.286 4.329 mhz 4.3mhz bell characteristics-1 vblrc t18 t20 t18 = 4.286mhz, 200mvp-p, bias = 4.6v sw20 = on (3.9k pull-down) measure during other timing than v-sync 92 110 132 mvp-p 4.3mhz bell characteristics-2 gblrl t18 t20 same condition as above. however, frequency of t18 is fblr-250khz measure t18 ratio to vblrc -7.5 -6.5 -5.5 db 4.3mhz bell characteristics-3 gblrh t18 t20 same condition as above. however, frequency of t18 is fblr+250khz -7.5 -6.5 -5.5 db anti-bell center frequency feqr t12 t11 sw11 = on (3.9k pull-down) ( see notes-3 ) t12 = 1 to 2mhz, 200mvp-p, bias = 4.6v measure during other timing than v-sync 1.0608 1.0715 1.0822 mhz anti-bell characteristics-1 veqrc t12 t11 same condition as above. however, frequency of t12 is 1.0715mhz 14 18 22 mvp-p anti-bell characteristics-2 geqrl t12 t11 same condition as above. however, frequency of t12 is feqr-62.5khz measure t12 ratio to veqrc 5.0 6.0 7.0 db anti-bell characteristics-3 geqrh t12 t11 same condition as above. however, frequency of t12 is feqr+62.5khz 5.0 6.0 7.0 db rec chroma signal output level vor t16 t12 t1 = 5v, t16 = 4.4mhz, 200mvp-p 144 180 220 mvp-p chroma spurius spectrum-1 gsr1 t16 t12 same condition as above. measure 2.2mhz ratio to vor at t12 -40 -30 db chroma spurius spectrum-2 gsr2 t16 t12 same condition as above. measure 3.3mhz ratio to vor at t12 -36 -30 db sync gate start time trgb t16 t12 1.1 1.6 2.1 s sync gate release time trge t16 t12 t1 = 5v, t9 = 5v ( see notes-7 ) t16 = 4.286mhz, 200mvp-p 3.6 4.1 4.6 s bgp-1 start time tbgb1 t29 t28 t9 = 5v ( see notes-10 ) 5.7 6.2 6.7 s bgp-2 start time tbgb2 t29 t28 same condition as above. however, t4 = 5v 6.1 6.6 7.1 s bgp-3 start time tbgb3 t29 t28 5.3 5.8 6.3 s bgp width tbgw t29 t28 same condition as above. however, t4 = 0v ( see notes-10 ) 2.3 2.8 3.3 s secam det outout resistance r26 t28 t27 = 5v ( see notes-11 ) 7 10 13 k ? secam det characteristics-1 vscmr1 t16 t28 t16 = secam color-bar ( see notes-12 ) 4.5 v secam det characteristics-2 vscmr2 t16 t28 t16 = pal color-bar ( see notes-13 ) 0.5 v regulator voltage vreg t13 3.8 4.0 4.2 v continued on next page.
LA70100M no.7204-3/16 continued from preceding page. ratings parameter symbol in out conditions min typ max unit forced secam mode control voltage range vthsm t1 t16 t12 t27 = 3v t16 = 4.286mhz, 200mvp-p measure voltage range of t1 when signal output from t12. 4.0 4.2 v cc v forced except-secam mode control voltage range vthmm t1 t16 t12 t27 = 4v t16 = 4.286mhz, 200mvp-p measure voltage range of t1 when t12 is mute. 0 0.5 1.0 v playback mode ( t2 = 4.43mhz, 400mvp-p t29 = comp.sync t17 = 5v, t10/t4 = open ) pb mode current drain iccp t14 t23 t24 t14 = 1.0715mhz, 50mvp-p 48 60 72 ma agc characteristics-1 vagc t14 t12 t14 = 1.0715mhz, 50mvp-p t9=5v, t1=5v voltage of t15 is v15r. 90 120 150 mvp-p agc characteristics-2 gagc1 t14 t12 same condition as above. however, level of t14 is 100mvp-p measure t14 ratio to vagc -1 0 1 db agc characteristics-3 gagc2 t14 t12 same condition as above. however, level of t14 is 25mvp-p -1 0 1 db 1.1mhz bpf characteristics-1 gf1l t14 t12 v15 = v15r ( see notes-4 ) t14 = 500khz, 50mvp-p measure t14 ratio to vagc -3 0 3 db 1.1mhz bpf characteristics-2 gf1h1 t14 t12 same condition as above. however, frequency of t14 is 2.2mhz -30 -20 db 1.1mhz bpf characteristics-3 gf1h2 t14 t12 same condition as above. however, frequency of t14 is 3.3mhz -35 -25 db 1.1mhz bell center frequency feqp t14 t11 t15 = v15r ( see notes-4 ) t14 = 1 to 1.2mhz, 50mvp-p ( see notes-5 ) sw11 = on (3.9k pull-down) measure during other timing than v-sync 1.0608 1.0715 1.0822 mhz 1.1mhz bell characteristics-1 veqpc t14 t11 same condition as above. however, frequency of t14 is 1.0715mhz 80 100 120 mvp-p 1.1mhz bell characteristics-2 geqpl t14 t11 same condition as above. however, frequency of t14 is feqp-62.5khz measure t14 ratio to veqpc -6.5 -5.5 -4.5 db 1.1mhz bell characteristics-3 geqph t14 t11 same condition as above. however, frequency of t14 is feqp+62.5khz -6.5 -5.5 -4.5 db anti-bell center frequency-1 fblp1 t18 t20 ( see notes-6 ) t18 = 4 to 5mhz, 200mvp-p, bias = 4.6v 4.243 4.286 4.329 mhz anti-bell center frequency-2 fblp2 t18 t20 same condition as above. however, t10 = 0v 4.283 4.326 4.619 mhz anti-bell center frequency-3 fblp3 t18 t20 same condition as above. however, t10 = 5v 4.323 4.366 4.659 mhz anti-bell characteristics-1 vblpc t18 t20 t18 = 4.286mhz, 200mvp-p, bias = 4.6v 32 40 48 mvp-p anti-bell characteristics-2 gblpl t18 t20 same condition as above. however, frequency of t18 is fblp1-250khz measure t18 ratio to vblpc 5.0 6.0 7.0 db anti-bell characteristics-3 gblph t18 t20 same condition as above. however, frequency of t18 is fblp1+250khz measure t18 ratio to vblpc 5.0 6.0 7.0 db pb chroma signal output level vop t14 t18 t1 = 5 v, t14 = 1.0715mhz, 50mvp-p 105 130 160 mvp-p chroma spurius spectrum-1 gsp1 t14 t18 same condition as above. however,. measure 2.2mhz ratio to vop at t18 -45 -35 db chroma spurius spectrum-2 gsp2 t14 t18 same condition as above. however,. measure 3.3mhz ratio to vop at t18 -28 -20 db sync gate start time tpgb t14 t18 1.2 1.7 2.3 s sync gate release time tpge t14 t18 t1 = 5v, t9 = 5v ( see notes-9 ) t14 = 1.0715mhz, 50mvp-p 4.7 5.2 5.7 s phase det output voltage-1 vscpd1 t14 t25 t26 t14 = 1.0625/1.1016mhz, 50mvp-p ( see notes-14 ) 150 180 mv phase det output voltage-2 vscpd2 t14 t25 t26 t14 = 627khz, 50mvp-p. (see notes-14) 100 mv continued on next page.
LA70100M no.7204-4/16 continued from preceding page. ratings parameter symbol in out conditions min typ max unit secam detection characteristics-1 vscmp1 v25 v26 t28 ( see notes-15 ) 4.5 v secam detection characteristics-2 vscmp2 v25 v26 t28 ( see notes-15 ) 0.5 v r/p control threshold voltage vtrp t17 minimum voltage of t16 under normal pb condition 2.3 2.5 2.7 v clock input level vclk t2 t9 t2 = sign wave (4.433619mhz), sw9 = on minimum voltage of t9 at phase locked t2 with t8. 100 200 800 mvp-p sync signal input threshold level vths t29 t28 minimum voltage of t29 at bgp outputs normally from t28. t9 = 5v 1.8 2.0 2.2 vp-p secam det comparator threshold voltage vtcomp t27 t28 minimum applied voltage of t27 at t28 = h. 3.2 3.5 3.8 v supplemental description (note 1) rec mode bell center fre quency (fblr1, fblr2, fblr3) : input a sine wave (200mvpp, 4 to 5mhz) to t16 and measure the amplitude at t20. assign to fblr1 (t10=open), fblr2 (t10=0v), fblr3 (t10=5v) the frequency at t16 where the amplitude is maximized. (note 3) rec eq (1.1mhz a-bell) center frequency (feqr) : observe the waveform at t11 when t12=sine wave (200mvpp, 4 to 5mhz, bias=4v) is input and assign to feqr the frequency at t11 where the amplitude is minimized. (note 4) assign to v15r the voltage of t15 at the time of vagc measurement. (note 5) pb eq (1.1mhz bell) center frequency (feqp) : input a sine wave (50mvpp, 1 to 1.2mhz) to t14 and assign to feqp the frequency at t14 where the signal level of t11 is maximized. (note 6) pb 4.3mhz a-bell center frequency (1 fblp1) / (2 fblp2) / (3 fblp3) : input a sine wave (200mvpp, 1 to 1.2mhz, bias=4v)) to t18 and assign to fbqp1 (t10=open), fbqp2 (t10=0v), fbeqp3 (t10=5v) the frequency at t1 8 where the signal level at t20 is minimized. secam standard color bar signal (75%) fig.1 d r d b t29 1.5 t16 4.40625mhz 214.5mvpp 4.25mhz 166.7mvpp
LA70100M no.7204-5/16 (note 7) rec mode sync gate start time, release time (trgb, trge) : input copm. sync to t29 and assume the sync gate start time (trgb) as the time from which the signal at t12 attenuates until the signal at t29 rises and assume the sync gate release time (trge) as the time from which the horizontal sync signal rises till the signal at t12 increases (fig. 2). (note 9) pb mode sync gate start time, release time (trgb, tpge) : input comp.sync to t29 and assume the sync gate start time (trgb) as the time from which the siganl at t18 attenuates until the horizontal sync signal rises and assume the sync gate release time (tpge) as the time from which the horizontal sync signal rises until the signal at t18 starts increasing. (note 10) bgp start time, bgp width (fig. 4) t9=5v (test mode) t29 (c.sync) t18 (pb-out) tpge tpgb 64
LA70100M no.7204-6/16 (note 11) output impedance of secam det (r28) assign to v28 as when generating 100 a from pin 28 by adding 5v to pin 27 and take ?h?, and calculate r28. (note 12) the sync signal at t29 must lag behind the secam color bar signal synchronization by 1.5 s (fig. 1). (note 13) the sync signal at t29 must lag behind the pal color bar signal synchronization by 1.5 s (fig. 6). (note 14) pb mode phase detection output differential voltage : vsapd1 : assign to vpd1 the dc voltage at t25 when a sine wave of 1.0625mhz is input to t14 and vpd2 the dc voltage at t26 when a sine wave of 1.1016mhz is input. vscpd1=vpd2 - vpd1 vsapd2 : assign to vpd3 and vpd4 the voltage at t25 and t26, respectively, when a sine wave of 627khz is input to t14. vscpd2=vpd4 - vpd3 (note 15) pb mode secam detection characteristics vscmp1 / vscmp2 : vscmp1 : apply the above-mentioned vpd1 and vpd2 to t2 5 and t26, respectively and measure the voltage at t28. vscmp2 : apply the above-mentioned vpd3 and vpd4 to t2 5 and t26, respectively and measure the voltage at t28. pal color bar signal fig.6 t29 1.5
LA70100M no.7204-7/16 functional description (1) rec mode video signals which have been input to pin 16, pass through th e 4.3mhz bpf with unnecessary component (ex. sync signal) removed, and the component of chroma signal is extracted. and the characteristics during transmission are made flat through a 4.3mhz-bell filter. the center frequency of this filter has automatically been adjusted to be 4.286mhz. after that, the limiter amplifier limits the amplitude, and the chroma signal frequency is converted to 1/4 by a divide-by-four circuit. though the limiter amplifier amplifies the noise of non-signal parts of the converted signal during synchronization, the sync gate cir cuit cleans the peripherals of the sync signal. still more, since th is signal has rectangle wavefo rms, it contains unnecessary component of frequency. to remove it, the signal passes through a 1.1mhz bpf and then is in put to 1.1mhz-a-bell filter. the center frequency of this filter is automatically adjust ed to 1.0715mhz, and has oppo site characteristics to bell characteristics. afterwards, unnecessary components around the sync signal are muted, low-band chroma signal is output to pin 12 through a buffer. (2) pb mode the low chroma signal that has been input from pin 14 enters agc amplifier and is controlled so that the output level of 4 times multiplier be constant. then it passes through the 1.1mhz bpf with unnecessary components removed before input to 1.1mhz-bell filter. the center frequency of this filter has automatically been adjusted to be 1.0715mhz. next, this signal passes through the 4 times multiplier composed of a 2 multiplier + 2.2 mhz bpf + 2 multiplier + 2.2mhz trap + 4.3mhz bpf with unnecessary component of frequency generated in multiplier removed. the first 2 multiplier has auto carrier leak balancer allowing beat obstruction reduced. next, this signal is limited pulse amplitude by limiting amplifier, then noises around the sync signal owing to limited amplifier are cleaned by the sync gate circuit. this si gnal has a rectangle waveform and contains unnecessary components of frequency. to remove it, the signal passes through a 4.3mhz bpf before input to 4.3mhz-bell filter. the center frequenc y of this filter is automatically adju sted to 4.286mhz, allowing the bell characteristics to the state during transmission. afterwards, unnecessary components around the sync signal are muted, low-band chroma signal is output to pin 18 through a buffer. 4.3mhz bpf 4.3mhz bell 20 16 lim 1/4 divider sync gate 1.1mhz bpf rec mute 19 1.107mhz 4.286mhz low chroma signal output video signal input monitor output fig.1 signal flow in rec mode 11 monitor output 1.1mhz a-bell 12 pb bell 11 monitor output 1.1mhz bpf low chroma signal input 1.107mhz agc amp 14 15 agc det 2.2mhz trap lim 19 vm x2 2.2mhz bpf x2 4.286mhz 20 monitor output sync gate pb mute 18 pb chroma signal output fig.2 signal flow in pb mode 4.3mhz bpf 4.3mhz bpf 4.3mhz a-bell
LA70100M no.7204-8/16 (3) clk input, afc input a frequency of 4.433619mhz sine wave or rectangle wavefo rm signal of pal fsc to clk input terminal. this signal is used for automatically adjusting the bell filter and genera ting timing pulse for afc and for sync gate. afc circuit automatically adjusts the frequen cy characteristics for each bpf . (4) sync gate circuit vertical sync signal is extracted by a synchronous separate circuit from composite sync signal that has been input from pin 29, and is conducted to bell/a-bell filter automatic adjus ting circuit. additionally, sync gate pulse and sample hold pulse are generated by the logic circuit. (5) bgp generator circuit bgp is used for killer circuit in rec mode, agc circuit in pb mode, and secam discrimination circuit. in bp mode, agc circuit detects the scale of the signal of bgp duration (id) so that the output of 4 times multiplier circuit b e constant. in secam discrimination circuit, bgp is used for making the s/h pulse (sp9, sp2 in figure 9) mentioned later. controlling pin 4 can convert the timing for composite sync that is input to pin 27. the width of bgp is determined by the constant of the inside of ic to about 2.5 s. and bgp timing can be monitored by pin 28 in test mode (pin 9 voltage = 5v). for bell adjust clock 4.43mhz vco afc buff 2 4.43mhz clock for each filter adjust 3 fig.3 29 sync sepa composite sync control logic 4.43mhz clock c.sync v.sync bell adjust secam det sample hold-3 sync gate/mute secam det sample hold-1, 2 c.sync v-mute bell adjust gate fig.4 c.sync sync gate mute 700 s
LA70100M no.7204-9/16 (6) rec-bell filter, pb-a-bell filter 4.3mhz a-bell filter characteristics 4.3mhz bell filter characteristics it is an internal filter of which center frequency is fitted to 4.286mhz by automatic adjusting circuit (described later) that uses input frequency (fsc), thus prevents this filter from affected by external components. (7) rec-a-bell filter, pb-bell filter 1.1mhz a-bell characteristics 1.1mhz bell characteristics it is an internal filter of which center frequency is fitted to 1.0715mhz by automatic adjusting circuit (described later) that uses input frequency (fsc), thus prevents this filter from affected by external components. (8) bell/a-bell filter frequen cy automatic adjustment control logic programable counter divider mode control 4.286mhz bell/a-bell osc enable gate clock for count up clock for count down difference d0 control clock for count down clock for count up mode control fig.8 (a) voltage control up/down counter up/down counter 4.43mhz clock c.sync v.sync gate difference divider programable counter divider divider 1.0715mhz bell/a-bell osc d1 d2 d3 d4 d5 control voltage control d0 d1 d2 d3 d4 d5
LA70100M no.7204-10/16 during a period when the color signal processing is left untouched (for about 700 s from the start of vertical sync signal), center frequency of bell filter is automa tically adjusted. mode control sets each bell/a-bell filter into vco mode after vertical sync signal is input, then the osc oscillates at 4.3mhz or 1.1mnz. oscillation output is divided respectively by a programmable divider and outputs the timing pulse that corresponds to oscillation frequency with control logic. this pulse is compared with the timing pules acquired by dividing 4.43mhz clk and generates up or down clk corresponding to the amount of discrepancies for oscillation fre quency 4.286mhz/1.0715mhz. that is input to up/down counter to increase and decrease the counter value. when enable pulse is generated the outputs d0 to d5 are rewritten, and the control voltage varies so that the oscillation frequency approach 4.286mhz/1.0715mhz. this operation repeats whenever the vertical sync signal is input and stops when the frequency difference becomes to a specified value ( 43khz / 10.7khz ). (9) secam the color signal with the amplitude limited by limiting circu it varies the phase according to the signal frequency after it passes through a 4.3mhz bpf. dc voltage according to the phase can be acquired by shifting this output phase by further 90 and inputting it to a phase detector with the original signal. th e characteristic of the output of a phase detector is as shown in the figure 9 (b), as the voltage limiting circuit operates at s/h-3 in order to prevent the malfunction caused by unwanted signals. this limiting circuit voltage is the phase detector outp ut dc voltage to which the signals of 4.286mhz vco is input used on bell filter automatic adjusting circ uit. then it is possible to operate the limiting circuit exactly at a frequency mor e than 4.286 mhz and to prevent the false discrimination during mesecam signal input. after that, input to two sample & hold circuits, the sampling pulse is shown like pulses correspond to bgp of ntsc and pal generated every 1h as sp1 and sp2 in figure 9 (b). the secam color signal has id signals of 4.25mhz and 4.40625mhz generated every 1h on the part that corresponds to this bgp, each phase detection output causes the level differ ence as v1, v2 in figure 9 (b). when this difference is sampled by sp1 and sp2 the waveform becomes as vs1 and vs2 in the figure 9 (b), and when it is hold by external capacitor it becomes as v1 and v2 . input to a comparator after detecti ng the difference of these two voltages, smoothing it to stable with the external capacitor connected to pin 27. in addition, applying more than 1v dc voltage to pin 30 allows the amplification of the level difference to be varied. when the smooth value of v1-v2 exceeds 3. 5v, secam signal is detected with a high-level output from the pin 28. this discrimination circuit uses a rule that the output of a phase detector differs every 1h as shown in the figure 9 (b) (c) to det ect a secam signal. pal signal always outputs high since its burst is constant and doesn?t vary phase detection output. comp logic vref ctl secam det out s/h-3 4.3mhz bpf 90 deg phase det lim from main signal line s/h-2 s/h-1 bell adjust pulse 28 sample hold pulse 27 25 21 sens control 30 sample hold pulse 26 s/h-2 fig.9(a) s/h-3 + det s/h-1 + 128 s sp1 sp2 sp3 same as esosc at fig.8 (b) vs1 vs2 v1 v2 chroma signal fig.9 (b) 4.25mhz (4.28mhz) 4.40625mhz v1 v2 vl frequency voltage fig.9 (c) c.sync vd enosc 4.3mhz/1.1mhz osc enable fig.8 (b) 700
LA70100M no.7204-11/16 mode control [ output mute control ] forcibly applying a dc voltage to pin-1 allows rec-out and pb-out muting control. pin-1 voltage output mode ( pin-12, pin-18 ) 5v forced secam open auto ( internal detect ) secam : active except secam : mute 0v forced mute [ test mode control ] pin use monitor output use monitor input pin-11 1.1mhz bell/a-bell (11 to gnd:3.9k) ? pin-12 1.1mhz bpf (pin-9 : 5v) 1.1mhz bell/a-bell input (4v bias+sig) pin-18 4.3mhz bpf (pin-9 : 5v) 4.3mhz bell/a-bell input (4v bias+sig) pin-20 4.3mhz bell/a-bell (20 to gnd:3.9k) ? pin-28 bgp out (pin-9 : 5v) ? [ bgp position control ] [ 4.3m bell offset control* ] pin-4 add voltage bgp position pi n-10 add voltage offset frequency l (0v) -400ns l (0v) +40khz open (2.5v) 0ns open (2.5v) 0khz h (5v) +400ns h (5v) +80khz *active only in pb mode [ rec / pb mode control ] pin-17 add voltage mode l (0v) rec mode h (5v) pb mode block diagram / application mode clk in a fc filter sync gate gen / v-sep mode ctl to mute control logic mode ctl h:secam m:auto det l:except secam 0.01 f 0.01 f 4.43mhz cw bgp delay + no connect bal c.sync in secam hi + s/h c2 s/h c1 secam det bgp gen to mute to sync gate to pb agc to rec killer 4.43mhz vco afc filter adj. buffer det c sync-in 2200 p f 2.2 secam det sens secam- det out gnd fo ctl rec mut pb-c in buffe r reg 4.0v bell monit1 rec-out reg pb-in + a gc filter agc amp agc det anti bell 2.2mh z rec pb bell 1.1mhz bfp pb rec sync gate 1/4 2.2mhz trap 2.2mhz bfp x2 4.3mhz bfp lim rec pb chroma 1.1mhz s/h c3 + 4.3mhz bell anti bell test mode vco monit 4.3mhz bell fo ctl bell monit4 lim exc pb-out buffe r pb mute 2.2mhz trap rec / pb pb-h a nti bell pb sync gate 4.3mhz bfp rec-in rec pb x2 no connect rec in rp ctl pb out bell rec v cc 5v v cc 2 gnd2 4.3mhz bell fo ctl h:+80 k m: 0k l: +40k * pb only 0.1 f 0.47 f + bgp delay ctl h:+400n m:0n l:-400n 1k ? 1 f rec : 0v pb : 5v 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0.01 f 0.47 f rec-c out v cc 5v 2200 p f v cc 0.01 f 0.01 f 1.1mhz bell anti bell
LA70100M no.7204-12/16 pin description pin no. pin name dc voltage signal waveform input/output form note 1 mode ctl 2.5v dc 2 clk in 2.5v 4.43mhz, 400mvp-p 3 afc filter 3.5v dc 4 bgp delay 1 to 5v dc 5 no connect 6 bal ( balancer ) 1.2v dc 7 gnd2 0v 8 gnd 0v 9 test mode ( vco monitor ) 2.1v normal : dc vco monitor : cw (4.43mhz, 450mvp-p) normal : open vco monitor : insert resistor to gnd test mode on : pull-up to v cc continued on next page. v cc 10k ? 100k ? 1 100k ? v cc 20k ? 500 ? 5k ? 2 20k ? 200 ? 1k ? 3 200 ? 7k ? 60k ? v cc 4.0v v cc 4 2k ? 50k ? 50k ? 6 v cc 2k ? 2k ? 500 ? 20k ? 1k ? 200 ? v cc 9 30k ? 200 ?
LA70100M no.7204-13/16 continued from preceding page. pin no. pin name dc voltage signal waveform input/output form note 10 f0 ctl (4.3mhz bell offset) 2.5v dc 11 bell monit 1 (1.1mhz bell monit) 2.7v normal : dc bell monitor : cw (1.1mhz, 300mvp-p) normal : open bell monitor : insert resistor to gnd 12 rec out ( test sig i/o ) rec : 2.2v pb : gnd 1.1mhz, 700mvp-p test input : signal with 4v bias 13 reg 4.0v dc 14 pb in 2.5v 1.1mhz, 50mvp-p 15 agc filter v cc /2 vbe dc 16 rec in 2.5v composite video 1.0vp-p continued on next page. v cc 10k ? 100k ? 100k ? 10 v cc 500 ? 11 500 ? 200 ? v cc 100 ? 1k ? 12 20k ? v cc 13 1k ? v cc 2k ? 10k ? 14 v cc 25k ? 2k ? 2k ? 8k ? 3k ? 15 v cc 10k ? 8k ? 1k ? 1k ? 16
LA70100M no.7204-14/16 continued from preceding page. pin no. pin name dc voltage signal waveform input/output form note 17 r/p ctl 0 to v cc dc vth = v cc /2 18 pb out ( test sig i/o ) pb : 1.95v rec : gnd 4.3mhz, 400mvp-p test input : signal with 4v bias 19 lim exc 2.3v dc 20 bell monit 4 (4.3mhz bell monit) 2.7v normal : dc bell monitor : cw (4.3mhz, 400mvp-p) normal : open bell monitor : insert resistor to gnd 21 s/h c3 2.5v dc (when connecting capacitor) 22 no connect 23 v cc 5v dc 24 v cc 2 5v dc 25 s/h c1 2.5v dc (when connecting capacitor) continued on next page. 1k ? v cc 17 200 ? v cc 100 ? 1k ? 18 20k ? v cc 1k ? 20k ? 10pf 19 v cc 500 ? 20 500 ? v cc 2k ? 10k ? 1k ? 21 v cc 2k ? 10k ? 1k ? 25
LA70100M no.7204-15/16 continued from preceding page. pin no. pin name dc voltage signal waveform input/output form note 26 s/h c2 2.5v dc (when connecting capacitor) 27 det c 2 to 5v dc secam det out dc (0v or 5v) normal mode 28 (bgp monitor ) 0v/5v bgp pulse at test mode 29 sync in threshold voltage 2.0v 30 secam det sens 2.0v dc v cc 2k ? 10k ? 1k ? 26 2 k ? 30 k ? 30 k ? 1k ? 1k ? 20k ? v cc 27 v cc 2 k ? 30 k ? 29 10 k ? v cc 28 5v 0v composite sync v cc 1 k ? 50k ? 30 30k ? 20 k ?
LA70100M no.7204-16/16 ps specifications of any and all sanyo semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides i nformation as of september, 2002. specificati ons and information her ein are subject to change without notice.

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